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2010 Microchip Technology Inc.

DS39616D-page 49

PIC18F2331/2431/4331/4431

5.2

Master Clear (MCLR)

The MCLR pin can trigger an external Reset of the

device by holding the pin low. These devices have a

noise filter in the MCLR Reset path that detects and

ignores small pulses.

The MCLR pin is not driven low by any internal Resets,

including the Watchdog Timer.

In PIC18F2331/2431/4331/4431 devices, the MCLR

input can be disabled with the MCLRE Configuration

bit. When MCLR is disabled, the pin becomes a digital

input. For more information, see Section 11.5

“PORTE, TRISE and LATE Registers”

5.3

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when-

ever VDD rises above a certain threshold. This allows

the device to start in the initialized state when VDD is

adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 k

to 10 k) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. The minimum rise rate

for VDD is specified (Parameter D004). For a slow rise

time, see Figure 5-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters (such

as voltage, frequency and temperature) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

Power-on Reset events are captured by the POR bit

(RCON<1>). The state of the bit is set to ‘0’ whenever

a POR occurs and does not change for any other Reset

event. POR is not reset to ‘1’ by any hardware event.

To capture multiple events, the user manually resets

the bit to ‘1’ in software following any Power-on Reset.

FIGURE 5-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

5.4

Brown-out Reset (BOR)

A Configuration bit, BOREN, can disable (if clear/

programmed) or enable (if set) the Brown-out Reset

circuitry. If VDD falls below VBOR (Parameter D005A

through D005F) for greater than TBOR (Parameter 35),

the brown-out situation will reset the chip. A Reset may

not occur if VDD falls below VBOR for less than TBOR.

The chip will remain in Brown-out Reset until VDD rises

above VBOR. If the Power-up Timer is enabled, it will be

invoked after VDD rises above VBOR; it then will keep

the chip in Reset for an additional time delay TPWRT

(Parameter 33). If VDD drops below VBOR while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be

initialized. Once VDD rises above VBOR, the Power-up

Timer will execute the additional time delay. Enabling

the Brown-out Reset does not automatically enable the

PWRT.

Note:

The following decoupling method is

recommended:

1. A 1

F capacitor should be connected

across AVDD and AVSS.

2. A

similar

capacitor

should

connected across VDD and VSS.

Note 1:

External Power-on Reset circuit is

required only if the VDD power-up slope is

too slow. The diode, D, helps discharge

the capacitor quickly when VDD powers

down.

R < 40 k

is recommended to make

sure that the voltage drop across R does

not violate the device’s electrical

specification.

1 k will limit any current flowing

into MCLR from external capacitor, C, in

the event of MCLR/VPP pin breakdown,

due to Electrostatic Discharge (ESD) or

Electrical Overstress (EOS).

VDD

MCLR

PIC18FXXXX

VDD

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